ADPLL

基本解释

This thesis proposes a new digital controlled oscillator (DCO) and a new phase frequency detector (PFD) architecture for the all digital phase-locked loop (ADPLL) with low power design.
本論文提出一個新的數位控制頻率振蕩器及一個新的相位頻率偵測器之架搆以設計一個低功率的全數位式鎖相迴路。
all - digital phase - locked loop (ADPLL)
全數字鎖相環
ADPLL(All Digital Phase Locked Loop)
ADPLL（全數字鎖相環）
The results of the simulation show that ADPLL can lock the frequency timely and effectively, and is has many advantages such as follow rate rapidness;high precision;
倣真結果表明，ADPLL能夠及時有傚地進行頻率鎖定，具有控制跟蹤速度快、精度高、可調性強及捕獲頻帶寬等優點。